library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity assignment is
    port(
		clock: in std_logic;
        enable: in std_logic;
        reset: in std_logic;
		exhausted: out std_logic;
        a: out std_logic_vector(0 to 7)
    );
end assignment;
architecture assignment_behavior of assignment is
signal internal_assignment : std_logic_vector(0 to 7);
signal exhaust_temp : std_logic;

begin --architecture

process(enable, clock)

begin
internal_assignment <= internal_assignment;	

	if reset = '1' then
		internal_assignment <= "00000000";
		exhaust_temp <= '0';
		
	elsif rising_edge(clock) then
		
		if enable = '1' then
			internal_assignment <= internal_assignment + 1;
			
			if internal_assignment = "11111111" then
				exhaust_temp <= '1';
			end if;	
			
		else
			internal_assignment <= internal_assignment;
			exhaust_temp <= '0';
		end if;
		
	end if;
	
end process;

--output switching process
process(internal_assignment, exhaust_temp)
begin --process
	exhausted <= exhaust_temp;
	a <= internal_assignment;
end process;
	
end architecture assignment_behavior;